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high performance, digital output gyroscope ADXRS453 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features complete rate gyroscope on a single chip 300/sec angular rate sensing ultrahigh vibration rejection: 0.01/sec/ g excellent 16/hour null bias stability internal temperature compensation 2000 g powered shock survivability spi digital output with 16-bit data-word low noise and low power 3.3 v to 5 v operation ?40c to +105c operation ultrasmall, light, and rohs compliant two package options low cost soic_cav package for yaw rate (z-axis) response innovative ceramic vertical mount package (lcc_v), which can be oriented for pitch, roll, or yaw response applications rotation sensing in high vibration environments rotation sensing for industrial and instrumentation applications high performance platform stabilization general description the ADXRS453 is an angular rate sensor (gyroscope) intended for industrial, instrumentation, and stabilization applications in high vibration environments. an advanced, differential, quad sensor design rejects the influence of linear acceleration, enabling the ADXRS453 to offer high accuracy rate sensing in harsh envi- ronments where shock and vibration are present. the ADXRS453 uses an internal, continuous self-test architec- ture. the integrity of the electromechanical system is checked by applying a high frequency electrostatic force to the sense structure to generate a rate signal that can be differentiated from the base- band rate data and internally analyzed. the ADXRS453 is capable of sensing an angular rate of up to 300/sec. angular rate data is presented as a 16-bit word that is part of a 32-bit spi message. the ADXRS453 is available in a 16-lead plastic cavity soic (soic_cav) and an smt-compatible vertical mount package (lcc_v), and is capable of operating across a wide voltage range (3.3 v to 5 v). functional block diagram spi interface miso mosi sclk cs high voltage generation eeprom p ss cp5 av ss v x ldo regulator p dd dv ss dv dd av dd registers/memory band-pass filter fault detection temperature calibration decimation filter arithmetic logic unit phase- locked loop clock divider demod q filter q daq p daq hv drive self-test control 12-bit adc amplitude detect 09155-001 z-axis angular rate sensor ADXRS453 figure 1.
ADXRS453 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 4 ? thermal resistance ...................................................................... 4 ? rate sensitive axis ....................................................................... 4 ? esd caution .................................................................................. 4 ? pin configurations and function descriptions ........................... 5 ? typical performance characteristics ............................................. 7 ? theory of operation ........................................................................ 9 ? continuous self-test .................................................................... 9 ? mechanical performance ............................................................... 10 ? noise performance ......................................................................... 11 ? applications information .............................................................. 12 ? calibrated performance ............................................................. 12 ? mechanical considerations for mounting .............................. 12 ? application circuits ................................................................... 12 ? ADXRS453 signal chain timing ............................................. 13 ? spi communication protocol ....................................................... 14 ? command/response ................................................................. 14 ? device data latching ................................................................. 15 ? spi timing characteristics ....................................................... 16 ? command/response bit definitions ....................................... 17 ? fault register bit definitions ................................................... 18 ? recommended start-up sequence with chk bit assertion . 20 ? rate data format ............................................................................ 21 ? memory map and registers .......................................................... 22 ? memory map .............................................................................. 22 ? memory register definitions ................................................... 23 ? package orientation and layout information ............................ 25 ? solder profile............................................................................... 27 ? package marking codes ............................................................ 28 ? outline dimensions ....................................................................... 29 ? ordering guide .......................................................................... 30 ? revision history 1/11revision 0: initial version
ADXRS453 rev. 0 | page 3 of 32 specifications t a = t min to t max , p dd = 5 v, angular rate = 0/sec, bandwidth = f 0 /200 (~77.5 hz), 1 g , continuous self-test on. table 1. parameter test conditions/comments symbol min typ max unit measurement range full-scale range fsr 300 400 /sec sensitivity see figure 2 nominal sensitivity 80 lsb//sec sensitivity tolerance t a = ?40c to +105c ?3 +3 % nonlinearity 1 best fit straight line 0.05 % fsr rms cross-axis sensitivity 2 ?3 +3 % null accuracy t a = 25c 0.4 /sec t a = ?40c to +105c 0.5 /sec noise performance rate noise density t a = 25c 0.015 /sec/hz t a = 105c 0.023 /sec/hz low-pass filter cutoff (?3 db) frequency f 0 /200 f lp 77.5 hz group delay 3 f = 0 hz t lp 3.25 4 4.75 ms sensor resonant frequency f 0 13 15.5 19 khz shock and vibration immunity sensitivity to linear acceleration dc to 5 khz 0.01 /sec/ g vibration rectification 0.0002 /sec/ g 2 self-test see the continuous self-test section magnitude 2559 lsb fault register threshold compared to locstx register data 2239 2879 lsb sensor data status threshold compared to locstx register data 1279 3839 lsb frequency f 0 /32 f st 485 hz st low-pass filter cutoff (?3 db) frequency f 0 /8000 1.95 hz group delay 3 52 64 76 ms spi communications clock frequency 8.08 mhz voltage input high mosi, cs , sclk 0.85 p dd p dd + 0.3 v voltage input low mosi, cs , sclk ?0.3 p dd 0.15 v voltage output low miso, current = 3 ma 0.5 v voltage output high miso, current = ?2 ma p dd ? 0.5 v pull-up current cs , p dd = 3.3 v, cs = p dd 0.15 60 200 a cs , p dd = 5 v, cs = p dd 0.15 80 300 a memory registers see the memory register definitions section temperature register value at 45c 0 lsb scale factor 5 lsb/c quadrature, self-test, and rate registers scale factor 80 lsb//sec power supply supply voltage p dd 3.15 5.25 v quiescent supply current i dd 6.0 8.0 ma turn-on time power-on to 0.5/sec of final value 100 ms 1 maximum limit is guaranteed by anal og devices, inc., characterization. 2 cross-axis sensitivity specification does not include effects due to device mounting on a printed circuit board (pcb). 3 minimum and maximum limits are guaranteed by design.
ADXRS453 rev. 0 | page 4 of 32 absolute maximum ratings table 2. parameter rating acceleration (any axis, 0.5 ms) unpowered 2000 g powered 2000 g supply voltage (p dd ) ?0.3 v to +6.0 v output short-circuit duration (any pin to ground) indefinite operating temperature range lcc_v package ?55c to +125c soic_cav package ?40c to +125c storage temperature range lcc_v package ?65c to +150c soic_cav package ?40c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, for a device soldered in a printed circuit board (pcb) for surface-mount packages. table 3. thermal resistance package type ja jc unit 16-lead soic_cav (rg-16-1) 191.5 25 c/w 14-lead ceramic lcc_v (ey-14-1) 1 185.5 23 c/w 1 thermal resistance of the lcc_v package is for the vertical layout, not the horizontal layout. rate sensitive axis the ADXRS453 is available in two package options. ? the soic_cav package is for applications that require z-axis (yaw) rate sensing. ? the lcc_v (vertical mount) package is for applications that require x-axis or y-axis (pitch or roll) rate sensing and for applications that require z-axis (yaw) rate sensing. the package has leads on two faces such that it can be mounted vertically for pitch or roll sensing or horizontally for yaw sensing. see figure 2 for details. lcc_v package 09155-002 rate axis + rate axis + soic package 9 16 z-axis figure 2. rate signal increases with clockwise rotation esd caution
ADXRS453 rev. 0 | page 5 of 32 pin configurations and function descriptions ADXRS453 top view (not to scale) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sclk mosi av dd dv ss rsvd av ss rsvd cp5 09155-003 dv dd rsvd rsvd miso p dd p ss v x cs figure 3. pin configuration, 16-lead soic_cav table 4. pin function descriptions, 16-lead soic_cav pin no. mnemonic description 1 dv dd digital regulated voltage. see figure 26 for the application circuit diagram. 2 rsvd reserved. this pin must be connected to dv ss . 3 rsvd reserved. this pin must be connected to dv ss . 4 cs chip select. 5 miso master in/slave out. 6 p dd supply voltage. 7 p ss switching regulator ground. 8 v x high voltage switching node. see figure 26 for the application circuit diagram. 9 cp5 high voltage supply. see figure 26 for the applicatio n circuit diagram. 10 rsvd reserved. this pin must be connected to dv ss . 11 av ss analog ground. 12 rsvd reserved. this pin must be connected to dv ss . 13 dv ss digital signal ground. 14 av dd analog regulated voltage. see figure 26 for the application circuit diagram. 15 mosi master out/slave in. 16 sclk spi clock.
ADXRS453 rev. 0 | page 6 of 32 1234567 14 13 12 11 10 9 8 p dd p ss mosi dv ss cs v x rsvd av ss av dd miso dv dd sclk cp5 rsvd top view (not to scale) 09155-004 1234567 back view (not to scale) 09155-005 cp5 rsvd sclk dv dd miso av dd av ss 141312 11 10 98 v x rsvd cs dv ss mosi p ss p dd figure 4. pin configuration, 14 -terminal lcc_v (vertical layout) figure 5. pin configuration, 14-terminal lcc_v (horizontal lay out) table 5. pin function descriptions, 14-terminal lcc_v pin no. mnemonic description 1 av ss analog ground. 2 av dd analog regulated voltage. see figure 27 for the application circuit diagram. 3 miso master in/slave out. 4 dv dd digital regulated voltage. see figure 27 for the application circuit diagram. 5 sclk spi clock. 6 cp5 high voltage supply. see figure 27 for the applicatio n circuit diagram. 7 rsvd reserved. this pin must be connected to dv ss . 8 rsvd reserved. this pin must be connected to dv ss . 9 v x high voltage switching node. see figure 27 for the application circuit diagram. 10 cs chip select. 11 dv ss digital signal ground. 12 mosi master out/slave in. 13 p ss switching regulator ground. 14 p dd supply voltage.
ADXRS453 rev. 0 | page 7 of 32 typical performance characteristics 20 18 16 14 12 10 8 6 4 0 2 percent of population (%) ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 2.01.61.20.80.4 error (/sec) 09155-006 40 35 30 25 20 15 10 5 0 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 2.01.61.20.80.4 percent of population (%) error (/sec) 09155-009 figure 6. soic_cav null accuracy at 25c figure 9. lcc_v null accuracy at 25c 30 25 20 15 10 5 0 ?3.0 percent of population (%) error (/sec) 09155-007 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 30 25 20 15 10 5 0 ?3.0 ?2.5 ?2.0 ?1.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 percent of population (%) error (/sec) 09155-010 figure 7. soic_cav null drift over temperature figure 10. lcc_v null drift over temperature 25 20 15 10 5 0 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 percent of population (%) change in sensitivity (%) 09155-008 25 20 15 10 5 0 ?0.030 ?0.025 ?0.020 ?0.015 ?0.010 ?0.005 0.030 0.025 0.020 0.015 0.010 0.005 0 percent of population (%) change in sensitivity (%) 09155-011 figure 8. soic_cav sensitivity error at 25c figure 11. lcc_v sensitivity error at 25c
ADXRS453 rev. 0 | page 8 of 32 30 25 20 15 10 5 0 ?3 ?2 ?1 0 3 2 1 percent of population (%) error (%) 09155-012 figure 12. soic_cav sensitivity drift over temperature 1 0.1 0.01 0.001 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 averaging time (hours) root allan variance (/sec) 09155-013 figure 13. typical root allan variance at 40c 3 2 1 0 ?1 ?2 ?3 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature (c) null output (/sec) 09155-014 figure 14. null output over temperature, 16 devices soldered on pcb 45 40 35 30 25 20 15 10 5 0 percent of population (%) 09155-015 ?3 ?2 ?1 0 3 2 1 error (%) figure 15. lcc_v sensitivity drift over temperature 1 0.1 0.01 0.001 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 averaging time (hours) root allan variance (/sec) 09155-016 figure 16. typical root allan variance at 105c 3 2 1 0 ?1 ?2 ?3 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature (c) error (%) 09155-017 figure 17. sensitivity over temperature, 16 devices soldered on pcb
ADXRS453 rev. 0 | page 9 of 32 theory of operation the ADXRS453 operates on the principle of a resonator gyroscope. figure 18 shows a simplified version of one of four polysilicon sensing structures. each sensing structure contains a dither frame that is electrostatically driven to resonance. this produces the necessary velocity element to produce a coriolis force when the device experiences angular rate. in the soic_cav package, the ADXRS453 is designed to sense a z-axis (yaw) angular rate; the lcc_v vertical mount package orients the device such that it can sense pitch or roll angular rate on the same pcb. 09155-018 x y z figure 18. simplified gyroscope sensing structure when the sensing structure is exposed to angular rate, the resulting coriolis force couples into an outer sense frame, which contains movable fingers that are placed between fixed pickoff fingers. this forms a capacitive pickoff structure that senses coriolis motion. the resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. the quad sensor design rejects linear and angular acceleration, including external g -forces and vibration. this is achieved by mechanically coupling the four sensing structures such that external g -forces appear as common-mode signals that can be removed by the fully differential architecture implemented in the ADXRS453. the resonator requires 22.5 v (typical) for operation. because only 5 v is typically available in most applications, a switching regulator is included on chip. continuous self-test the ADXRS453 gyroscope implements a complete electro- mechanical self-test. an electrostatic force is applied to the gyroscope frame, resulting in a deflection of the capacitive sense fingers. this deflection is exactly equivalent to deflection that occurs as a result of external rate input. the output from the beam structure is processed by the same signal chain as a true rate output signal, providing complete coverage of both the electrical and mechanical components. the electromechanical self-test is performed continuously during operation at a rate higher than the output bandwidth of the device. the self-test routine generates equivalent positive and negative rate deflections. this information can then be filtered with no overall effect on the demodulated rate output. rate signal with continuous self-test signal. self-test amplitude. internally compared to the specification table limits. low frequency rate information. 09155-019 figure 19. continuous self-test demodulation t he difference amplitude between the positive and negative self-test deflections is filtered to f 0 /8000 (~1.95 hz) and is continuously monitored and compared to hard-coded self-test limits. if the measured amplitude exceeds these limits (listed in table 1 ), one of two error conditions is asserted, depending on the magnitude of the self-test error. ? for less severe self-test error magnitudes, the cst bit of the fault register is asserted. however, the status bits (st[1:0]) in the sensor data response remain set to 01 for valid sensor data. ? for more severe self-test errors, the cst bit of the fault register is asserted and the status bits (st[1:0]) in the sensor data response are set to 00 for invalid sensor data. table 1 lists the thresholds for both of these failure conditions. if desired, the user can access the self-test information by issuing a read command to the self-test memory register (address 0x04). see the spi communication protocol section for more informa- tion about error reporting.
ADXRS453 rev. 0 | page 10 of 32 mechanical performance the ADXRS453 has excellent shock and vibration rejection. figure 20 shows the output noise response of the ADXRS453 in a vibration free environment. figure 21 shows the response of the same device to 15 g rms random vibration (50 hz to 5 khz). as shown in figure 21 , no frequencies are particularly sensitive to vibration. response to vibration in all axes is similar. shock response is also excellent, as shown in figure 22 and figure 23 . figure 22 shows a 99 g input stimulus applied to each axis, and figure 23 shows the typical response to this shock in each axis. shock response of 0.01/sec/ g is apparent. 0.1 0.01 0.001 0.0001 55 0 frequency (hz) gyro output (/sec/ 5 0 0 hz) 09155-020 figure 20. ADXRS453 output noise response with no vibration applied 0.1 0.01 0.001 0.0001 55 0 frequency (hz) gyro output (/sec/ 5 0 0 hz) 09155-021 figure 21. ADXRS453 output noise response with 15 g rms random vibration (50 hz to 5 khz) applied 40 20 ?60 ?80 ?100 0 ?20 ?40 ?120 00 . 1 0 0.05 0.15 0.20 time (seconds) input stimulus ( g ) 09155-022 figure 22. 99 g shock input 10 8 2 ?2 ?4 ?6 ?8 0 6 4 ?10 00 . 1 0 0.05 0.15 0.20 time (seconds) gyro output (/sec) 09155-023 figure 23. typical output response due to 99 g shock (see figure 22 )
ADXRS453 rev. 0 | page 11 of 32 noise performance the ADXRS453 noise performance is very consistent from device to device and varies very predictably with temperature. table 6 contains statistical noise data at three temperature points for a large population of ADXRS453 devices (more than 3000 parts from several manufacturing lots). table 6. statistical noise data temperature noise (/sec/hz) mean standard deviation ?40c 0.0109 0.0012 +25c 0.0149 0.0015 +105c 0.0222 0.0019 noise increases fairly linearly with temperature, as shown in figure 24 . 0.050 0.045 0.030 0.020 0.015 0.010 0.005 0.025 0.040 0.035 0 ?50 50 0 100 150 temperature (c) noise density (/sec/ hz) 09155-024 figure 24. noise density vs. temperature, 16 devices
ADXRS453 rev. 0 | page 12 of 32 applications information calibrated performance the ADXRS453 gyroscope uses internal eeprom memory to store its temperature calibration information. the calibration information is encoded into the device during factory test. the calibration data is used to perform offset, gain, and self-test cor- rections over temperature. by storing this information internally, the ADXRS453 eliminates the need for the customer to perform system level temperature calibration. mechanical considerations for mounting mount the ADXRS453 in a location close to a hard mounting point of the pcb. mounting the ADXRS453 at an unsupported pcb location (that is, at the end of a lever or in the middle of a trampoline, as shown in figure 25 ) can result in apparent mea- surement errors because the gyroscope is subject to the resonant vibration of the pcb. locating the gyroscope near a hard mounting point helps to ensure that any pcb resonances at the gyroscope are above the frequency at which harmful aliasing with the internal electronics can occur. to ensure that aliased signals do not couple into the baseband measurement range, design the module so that the first system level resonance occurs at a frequency higher than 800 hz. mounting points pcb gyroscope 0 9155-025 figure 25. incorrectly placed gyroscope application circuits figure 26 and figure 27 show the recommended application circuits for the ADXRS453 gyroscope. these application circuits provide a connection reference for the available package types. note that dv dd , av dd , and p dd are all individually connected to ground through 1 f capacitors; do not connect these supplies together. in addition, an external diode and inductor must be connected for proper operation of the internal shunt regulator (see table 7 ). these components allow the internal resonator drive voltage to reach its required level. table 7. components for ADXRS453 application circuits component qty description inductor 1 470 h diode 1 >24 v breakdown voltage capacitor 3 1 f capacitor 1 100 nf 09155-026 1 8 9 16 dv dd rsvd rsvd cs miso p dd v x p ss sclk mosi av dd dv ss rsvd av ss cp5 rsvd 100nf 1f 1f 3.3v to 5v 1f diode >24v breakdown 470h gnd gnd gnd figure 26. recommended application circuit, soic_cav package 09155-027 av ss av dd miso dv dd sclk cp5 rsvd rsvd p dd p ss mosi dv ss v x 1f 1f 1f 100nf 3.3 v to 5v diode >24v breakdown gnd gnd 470h g nd 11 4 top view cs figure 27. recommended application circuit, lcc_v package
ADXRS453 rev. 0 | page 13 of 32 ADXRS453 signal chain timing the ADXRS453 primary signal chain is shown in figure 28 . the signal chain is the series of necessary functional circuit blocks through which the rate data is generated and processed. this sequence of electromechanical elements determines how quickly the device can translate an external rate input stimulus to an spi word that is sent to the master device. the group delay, which is a function of the filter characteristic, is the time required for the output of the low-pass filter to be within 10% of the external rate input. in figure 28 , the group delay is shown to be ~4 ms. additional delay can be observed due to the timing of spi transactions and the population of the rate data into the internal device registers. figure 28 illustrates this delay through each element of the signal chain. the transfer function for the rate data lpf is given as 2 1 64 1 1 ? ? ? ? ? ? ? ? ? ? ? ? z z where: (typ)khz16 11 == 0 f t (f 0 is the resonant frequency of the ADXRS453.) the transfer function for the continuous self-test lpf is given as () 1 6364 1 ? ? z where: (typ)ms1 16 == 0 f t ( f 0 is the resonant frequency of the ADXRS453.) z-axis angular rate sensor spi transaction registers/memory band-pass filter arithmetic logic unit demod miso mosi 12-bit adc primary signal chain <5s delay 4ms group delay <2.2ms delay <64ms group delay rate data lpf continuous self-test lpf <5s delay <5s delay 09155-028 figure 28. primary signal chain and associated delays
ADXRS453 rev. 0 | page 14 of 32 spi communication protocol command/response input/output is handled through a 32-bit command/response spi interface. with the command/response spi interface, the response to a command is issued during the next sequential spi exchange (see figure 29 ). the format for the interface is defined as follows: clock phase = clock polarity = 0 table 9 shows the commands that can be sent from the master device to the gyroscope. table 1 0 shows the responses to these commands from the gyroscope. for descriptions of the bits in the commands and responses, see the command/response bit definitions section and the fault register bit definitions section. the device response to the initial command is 0x00000001. this response prevents the transmission of random data to the master device upon the initial command/response exchange. the spi interface uses the ADXRS453 pins described in table 8 . table 8. spi signals signal pin description serial clock sclk exactly 32 clock cycles during cs active chip select cs active low chip select pin master out/ slave in mosi input for data sent to the gyroscope (slave) from the main controller (master) master in/ slave out miso output for data sent to the main controller (master) from the gyroscope (slave) mosi miso 32 clock cycles sclk cs command n response n ? 1 32 clock cycles command n + 1 response n 09155-029 figure 29. spi protocol table 9. spi commands bit command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sensor data sq1 sq0 1 sq2 chk p read 0 sm2 sm1 sm0 a8 a7 a6 a5 a4 a3 a2 a1 a0 p write 0 sm2 sm1 sm0 a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p table 10. spi responses bit command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sensor data sq2 sq1 sq0 p0 st1 st0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pll q nvm por pwr cst chk p1 read 0 1 0 p0 1 1 1 0 sm2 sm1 sm0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p1 write 0 0 1 p0 1 1 1 0 sm2 sm1 sm0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p1 r/w error 0 0 0 p0 1 1 1 0 sm2 sm1 sm0 0 0 spi re du pll q nvm por pwr cst chk p1
ADXRS453 rev. 0 | page 15 of 32 device data latching to allow for rapid acquisition of data from the ADXRS453, device data latching is implemented, as shown in figure 30 . when the chip select pin is asserted ( cs goes low), the data in the device is latched into memory. when the full mosi command is received and the chip select pin is deasserted ( cs goes high), the data is shifted into the spi port registers in preparation for the next sequential command/response exchange. device data latching allows for an extremely fast sequential transfer delay of 0.1 s (see ). table 11 note that the transmitted data is only as recent as the sequential transmission delay implemented by the system. conditions that result in a sequential transfer delay of several seconds cause the next sequential device response to contain data that is several seconds old. 32 clock cycles 32 clock cycles 32 clock cycles scl k mosi miso command n 0x? response n ? 1 0x00000001 response n 0x? response n + 1 0x? command n + 1 0x? command n + 2 0x? 0 9155-031 device data is latched after the assertion of cs. latched data is transmitted during the next sequential command/response exchange. cs figure 30. device data latching
ADXRS453 rev. 0 | page 16 of 32 s pi timing characteristics t he following conditions apply to the spi command/response timing characteristics in table 11 : ? all timing parameter are guaranteed through characterization. ? all timing is shown with respect to 10% dv dd and 90% of the actual delivered voltage waveform. ? parameters are valid for 3.0 v dv dd 5.5 v. ? capacitive load for all signals is assumed to be 80 pf. ? ambient temperature is ?40c t a +105c. ? the miso pull-up is 47 k or 110 a. table 11. spi command/respons e timing characteristics symbol min max unit description f op 8.08 mhz spi operating frequency t sclkh 1/2 t sclk ? 13 ns sclk high time t sclkl 1/2 t sclk ? 13 ns sclk low time t sclk 123.7 ns sclk period t f 5.5 13 ns sclk fall time t r 5.5 13 ns sclk rise time t su 37 ns data input (mosi) setup time t high 49 ns data input (mosi) hold time t a 20 ns data output (miso) access time t v 40 ns data output (miso) valid after sclk t lag_miso 0 ns data output (miso) lag time t dis 40 ns data output (miso) disable time t lead 1/2 t sclk ns enable ( cs ) lead time t lag_ cs 1/2 t sclk ns enable ( cs ) lag time t td 0.1 s sequential transfer delay cs 09155-030 s cl k t sclkh t sclkl t sclk t lead t f t r t lag_cs t td msb lsb miso t a t lag_miso t v t dis t high msb lsb mosi t su figure 31. spi timings
ADXRS453 rev. 0 | page 17 of 32 command/response bit definitions table 12. spi interface bit definitions bits description sq2 to sq0 sequence bits (from master) sm2 to sm0 sensor module bits (from master) a8 to a0 register address d15 to d0 data p command odd parity spi spi command/response re request error du data unavailable st1, st0 status bits p0 response, odd parity, bits[31:16] p1 response, odd parity, bits[31:0] sq2 to sq0 bits the sq2 to sq0 bits provide the system with a means of synchro- nizing the data samples that are received from multiple sensors. to facilitate correct synchronization, the ADXRS453 gyroscope includes the sq[2:0] bits in the response sequence as they were received in the request. sm2 to sm0 bits the sm2 to sm0 bits are the sensor module bits from the master device. these bits are not implemented in the ADXRS453 and are hard-coded to 000 for all occurrences. a8 to a0 bits the a8 to a0 bits represent the memory address for data read or data write. these bits should be supplied by the master when the memory registers are being accessed; these bits are ignored for all sensor data requests. for a complete description of the available memory registers, see the memory register definitions section. d 15 to d0 bits t he d15 to d0 bits are the 16-bit device data, which can contain any of the following: ? data from the master to be written to a memory register, as specified by the a8 to a0 bits. ? sensor rate output data from the slave. ? device data from the slave read from the memory register specified by the a8 to a0 bits, as well as the data from the next sequential register. ? following a write command, the 16-bit data that is written to the specified memory register in the ADXRS453 and is reflected back to the master device for correlation. p bit a parity bit (p) is required for all master-to-slave data transmis- sions. the communication protocol requires one parity bit to achieve odd parity for the entire 32-bit command. dont care bits are also factored into the parity calculation. spi bit t he spi bit is set when either of the following occurs: ? too many or not enough bits were transmitted. ? a message from the control module contains a parity error. a spi error causes the device to issue a r/w error response regardless of the spi command type issued by the master device (see table 10 ). in addition, any error during a sensor data request results in the device issuing a read/write error. re bit t he request error (re) bit is the communication error bit trans- mitted from the ADXRS453 device to the control module. request errors can occur when ? an invalid command is sent from the control module. ? a read/write command specifies an invalid memory register. ? a write command attempted to write to a nonwritable memory register. du bit after the chip select pin is deasserted ( cs goes high), the user must wait 0.1 s before reasserting the cs pin to initiate another command/response frame with the device. failure to adhere to this timing specification may result in a data unavailable (du) error. st1 and st0 bits the status bits (st1 and st0) are used to signal to the master device the type of data contained in the response message (see table 13 ). table 13. status bit code definitions st[1:0] contents of bits[d15:d0] 00 invalid data for sensor data response 01 valid sensor data 10 sensor self-test data 11 read/write response either of the following conditions can result in the st[1:0] bits being set to 00 during a sensor data response: ? the self-test response is sufficiently different from its nominal value (see the specifications section for the appropriate limits). ? the pll fault bit is active (see the pll bit section). p0 bit p0 is the parity bit that establishes odd parity for bits[31:16] of the device response. p1 bit p1 is the parity bit that establishes odd parity for the entire 32-bit device response.
ADXRS453 rev. 0 | page 18 of 32 fault register bit definitions table 14 describes the bits available for signaling faults to the user. the individual bits of the fault registers are updated asynchronously, depending on their respective detection criteria; however, it is recommended that the fault registers be read at a rate of at least 250 hz. when asserted, an individual status bit is not deasserted until it is read by the master device. if the error persists after a fault register read, the status bit is immediately reasserted and remains asserted until the next sequential command/ response exchange. the bits in the fault0 register are appended to every sensor data response (see table 10 ). both fault registers can be accessed by issuing a read command to address 0x0a. table 14. fault register bit definitions register bit name description fault1 fail failure that sets the st[1:0] bits to 00 amp amplitude detection failure ov regulator overvoltage uv regulator undervoltage fault0 pll phase-locked loop failure q quadrature error nvm nonvolatile memory fault por power-on or reset failed to initialize pwr power regulation failed due to over- voltage or undervoltage condition cst continuous self-test failure or amplitude detection failed chk check: generate faults fail bit the fail flag is asserted when the st[1:0] bits are set to 00 (see the st1 and st0 bits section). assertion of the fail bit indicates that the device has experienced a gross failure and that the sensor data could be invalid. amp bit the amp fault bit is asserted when the measured amplitude of the silicon resonator has been significantly reduced. this condition can occur if the voltage supplied to cp5 falls below the requirements of the internal voltage regulator. this fault bit is ored with the cst fault bit; therefore, during a sensor data request, the cst bit position represents either an amp failure or a cst failure. the full fault register can be read from memory to determine the specific failure. ov bit the ov fault bit is asserted if the internally regulated voltage (nominally 3 v) is observed to exceed 3.3 v. this measurement is low-pass filtered to prevent artifacts such as noise spikes from asserting a fault condition. when an ov fault occurs, the pwr fault bit is asserted simultaneously. because the ov fault bit is not transmitted as part of a sensor data response, it is recommended that the user read back the fault1 and fault0 memory registers upon the assertion of a pwr error to determine the specific error condition. uv bit the uv fault bit is asserted if the internally regulated voltage (nominally 3 v) is observed to be less than 2.77 v. this mea- surement is low-pass filtered to prevent artifacts such as noise spikes from asserting a fault condition. when a uv fault occurs, the pwr fault bit is asserted simultaneously. because the uv fault bit is not transmitted as part of a sensor data response, it is recommended that the user read back the fault1 and fault0 memory registers upon the assertion of a pwr error to determine the specific error condition. pll bit the pll bit indicates that the device has experienced a failure in the phase-locked loop functional circuit block. this occurs when the pll fails to achieve synchronization with the resonator structure. if the pll status flag is active, the st[1:0] bits of the sensor data response are set to 00, indicating that the response contains potentially invalid rate data. q bit a q fault is asserted based on two independent quadrature calculations. ? the quad memory register (address 0x08) contains a value corresponding to the total instantaneous quadrature present in the device. if this value exceeds 4096 lsb, a q fault is issued. ? an internal quadrature accumulator records the amount of quadrature correction performed by the ADXRS453. a q fault is issued when the quadrature error present in the device has contributed to an equivalent of 4/sec (typical) of rate offset. nvm bit an nvm error is transmitted to the control module when the internal nonvolatile memory data fails a checksum calculation. this check is performed once every 50 s and does not include the pidx memory registers. por bit an internal check is performed on device startup to ensure that the volatile memory of the device is functional. this is accom- plished by programming a known value from the device rom into a volatile memory register. this value is then continuously compared to the known value in rom every 1 s for the duration of the device operation. if the value stored in the volatile memory changes or does not match the value stored in rom, the por error flag is asserted. the value stored in rom is rewritten to the volatile memory upon a device power cycle.
ADXRS453 rev. 0 | page 19 of 32 pwr bit the device performs a continuous check of the internal 3 v regulated voltage level. if either an overvoltage (ov) or under- voltage (uv) fault is asserted, the pwr bit is also asserted. this condition occurs if the regulated voltage is observed to be either above 3.3 v or below 2.77 v. an internal low-pass filter removes high frequency glitching effects to prevent the pwr bit from being asserted unnecessarily. to determine whether the fault is a result of an overvoltage or undervoltage condition, the ov and uv fault bits must be read. cst bit t he ADXRS453 is designed with continuous self-test function- ality. the measured self-test amplitudes are compared to the limits presented in table 1 . deviations from these values result in reported self-test errors. the two thresholds for a self-test failure are as follows: ? self-test value > 512 lsb from nominal results in the assertion of the self-test flag in the fault register. ? self-test value > 1856 lsb from nominal results in the assertion of the self-test flag in the fault register and the setting of the st[1:0] bits to 00, indicating that the rate data contained in the sensor data response is potentially invalid. chk bit the chk bit is transmitted by the control module to the ADXRS453 as a method of generating faults. by asserting the chk bit, the device creates conditions that result in the gener- ation of all faults represented in the fault registers. for example, the self-test amplitude is deliberately altered to exceed the fault detection threshold, resulting in a self-test error. in this way, the device is capable of checking both its ability to detect a fault condition and its ability to report that fault condition to the control module. the fault conditions are initiated nearly simultaneously; how- ever, the timing for receiving fault codes when the chk bit is asserted depends on the time required to generate each unique fault. it takes no more than 50 ms for all internal faults to be generated and the fault register to be updated to reflect the condition of the device. until the chk bit is cleared, the status bits (st[1:0]) are set to 10, indicating that the data should be interpreted by the control module as self-test data. after the chk bit is deasserted, an additional 50 ms are required for the fault conditions to decay and for the device to return to normal operation. see the recommended start-up sequence with chk bit assertion section for the proper methodology for asserting the chk bit.
ADXRS453 rev. 0 | page 20 of 32 recommended start-up sequence with chk bit assertion figure 32 illustrates a recommended start-up sequence that can be implemented by the user. alternate start-up sequences can be used, but the response from the ADXRS453 must be handled correctly. if the start-up sequence is implemented immediately after power is applied to the device, the total time to implement the following fault detection routine is approximately 200 ms. as described in the device data latching section, the data present in the device upon the assertion of the cs signal is used in the next sequential command/response exchange. this results in an apparent one-transaction delay before the data resulting from the assertion of the chk bit is reported by the device. for all other read/write interactions with the device, no such delay exists, and the mosi command is serviced during the next sequential command/response exchange. note that if the chk bit is deasserted and the user tries to obtain data from the device before the cst fault flag clears, the device reports the data as error data. 0x20000000 0x20000000 0x20000003 0x20000000 another 50ms delay must be observed to allow the fault conditions to clear. if the device is functioning properly, the miso response contains all active faults, as well as having set the message format to self-test data. this is indicated through the st bits being set to 10. a 50ms delay is required so that the generation of faults within the device is allowed to complete. however, because the device data is latched before the chk bit is asserted, the device response during this command/response exchange does not contain fault information. this response can be discarded. when the 100ms start-up time has elapsed, the master device is free to assert the chk bit and start the process of internal error checking. during the first command/ response exchange after power-on, the ADXRS453 is designed to issue a predefined response. power is applied to the device. wait 100ms to allow for the internal circuitry to be initialized. the fault bits of the ADXRS453 remain active until cleared. due to the required decay period for each fault condition, fault conditions remain present upon the immediate deassertion of the chk bit. this results in a second sequential response in which the fault bits are asserted. again, the response is formatted as self-test data indicating that the fault bits have been set intentionally. all fault conditions are cleared, and all subsequent data exchanges need only observe the sequential transfer delay timing parameter. 0x?ff or 0x?fe (parity dependent) 0x?ff or 0x?fe (parity dependent) 0x? 0x00000001 mosi sclk cs miso 32 clock cycles 32 clock cycles 32 clock cycles 32 clock cycles 09155-032 data latch point mosi: sensor data request chk bit asserted miso: standard initial response mosi: sensor data request (this clears the chk bit) miso: sensor data response mosi: sensor data request miso: chk response st[1:0] = 10 mosi: sensor data request miso: chk response st[1:0] = 10 xx x t = 100ms t = 150ms t = 200ms t = 200ms + t td t = 200ms + 2 t td figure 32. recommended start-up sequence
ADXRS453 rev. 0 | page 21 of 32 rate data format the ADXRS453 gyroscope transmits rate data in a 16-bit format as part of a 32-bit spi data frame. see table 10 for the full 32-bit format of the sensor data response. the rate data is transmitted msb first, from d15 to d0. the data is formatted as a twos complement number with a scale factor of 80 lsb//sec. therefore, the highest obtainable value for positive (clockwise) rotation is 0x7fff (decimal +32,767), and the highest obtainable value for negative (counterclockwise) rotation is 0x8000 (decimal ?32,768). performance of the device is not guaranteed above 24,000 lsb (300/sec). table 15. rate data 16-bit rate data description decimal (lsbs) hex (d15:d0) +32,767 0x7fff maximum possible positi ve data value (not guaranteed) +24,000 0x5dc0 +300/sec rotation (positive fsr) +160 0x00a0 +2/sec rotation +80 0x0050 +1/sec rotation +40 0x0028 +0.5/sec rotation +20 0x0014 +0.025/sec rotation 0 0x0000 zero rotation value ?20 0xffec ?0.025/sec rotation ?40 0xffd8 ?0.5/sec rotation ?80 0xffb0 ?1/sec rotation ?160 0xff60 ?2/sec rotation ?24,000 0xa240 ?300/sec rotation (negative fsr) ?32,768 0x8000 maximum possible negative data value (not guaranteed)
ADXRS453 rev. 0 | page 22 of 32 memory map and registers memory map table 16 provides a list of the memory registers that can be read from or written to by the user. see the spi communication protocol section for the proper input sequence to read from or write to a specific memory register. each memory register has eight bits of data; however, when a read request is performed, the data always returns as a 16-bit message. this is accomplished by appending the data from the next sequential register to the memory address that was specified. data is transmitted msb first. for proper acquisition of data from the memory register, make the read request to the even-numbered register address only; for example, to read the locstx registers, address register 0x04, but not register 0x05. for a description of each memory register listed in table 16 , see the memory register definitions section. table 16. memory register map address register name d7 (msb) d6 d5 d4 d3 d2 d1 d0 (lsb) 0x00 rate1 rte15 rte14 rte13 rte12 rte11 rte10 rte9 rte8 0x01 rate0 rte7 rte6 rte5 rte4 rte3 rte2 rte1 rte0 0x02 tem1 tem9 tem8 tem7 tem6 tem5 tem4 tem3 tem2 0x03 tem0 tem1 tem0 unused unused unused unused unused unused 0x04 locst1 lcst15 lcst14 lcst13 lcst12 lcst11 lcst10 lcst9 lcst8 0x05 locst0 lcst7 lcst6 lcst5 lcst4 lcst3 lcst2 lcst1 lcst0 0x06 hicst1 hcst15 hcst14 hcst13 hcst12 hcst11 hcst10 hcst9 hcst8 0x07 hicst0 hcst7 hcst6 hcst5 hcst4 hcst3 hcst2 hcst1 hcst0 0x08 quad1 qad15 qad14 qad13 qad12 qad11 qad10 qad9 qad8 0x09 quad0 qad7 qad6 qad5 qad4 qad3 qad2 qad1 qad0 0x0a fault1 unused unused un used unused fail amp ov uv 0x0b fault0 pll q nvm por pwr cst chk 0 0x0c pid1 pidb15 pidb14 pidb13 pidb12 pidb11 pidb10 pidb9 pidb8 0x0d pid0 pidb7 pidb6 pidb5 pidb4 pidb3 pidb2 pidb1 pidb0 0x0e sn3 snb31 snb30 snb29 sn b28 snb27 snb26 snb25 snb24 0x0f sn2 snb23 snb22 snb21 sn b20 snb19 snb18 snb17 snb16 0x10 sn1 snb15 snb14 snb13 snb12 snb11 snb10 snb9 snb8 0x11 sn0 snb7 snb6 snb5 snb4 snb3 snb2 snb1 snb0
ADXRS453 rev. 0 | page 23 of 32 memory register definitions the spi-accessible memory registers are described in this section. as noted in the memory map section, when requesting data from a memory register, only the first sequential memory address should be addressed. the data returned by the device contains 16 bits of memory register information. bits[15:8] contain the msb of the requested information, and bits[7:0] contain the lsb. rate (ratex) registers addresses: 0x00 (rate1) 0x01 (rate0) register update rate: f 0 /32 (~485 hz) scale factor: 80 lsb//sec the ratex registers contain the temperature compensated rate output of the device, filtered to f 0 /200 (~77.5 hz). this data can also be accessed by issuing a sensor data read request to the device. the data is presented as a 16-bit, twos complement number. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 rte15 rte14 rte13 rte12 rte11 rte10 rte9 rte8 d7 d6 d5 d4 d3 d2 d1 d0 rte7 rte6 rte5 rte4 rte3 rte2 rte1 rte0 temperature (temx) registers addresses: 0x02 (tem1) 0x03 (tem0) register update rate: f 0 /32 (~485 hz) scale factor: 5 lsb/c the temx registers contain a value corresponding to the temperature of the device. the data is presented as a 10-bit, twos complement number. 0 lsb corresponds to a temperature of approximately 45c (see tabl e 17 ). msb lsb d15 d14 d13 d12 d11 d10 d9 d8 tem9 tem8 tem7 tem6 tem5 tem4 tem3 tem2 d7 d6 d5 d4 d3 d2 d1 d0 tem1 tem0 unused table 17. sample temperatures and temx register contents temperature value of tem1 and tem0 registers 1 45c 0000 0000 00xx xxxx 85c 0011 0010 00xx xxxx 0c 1100 0111 11xx xxxx 1 x = dont care. low cst (locstx) registers addresses: 0x04 (locst1) 0x05 (locst0) register update rate: f 0 /16 (~970 hz) scale factor: 80 lsb//sec the locstx registers contain the value of the temperature compensated and low-pass filtered continuous self-test delta. this value is a measure of the difference between the positive and negative self-test deflections and corresponds to the values presented in table 1 . the device issues a cst error if the value of the self-test exceeds the established self-test limits. the self-test data is filtered to f 0 /8000 (~1.95 hz) to prevent false triggering of the cst fault bit. the data is presented as a 16-bit, twos com- plement number, with a scale factor of 80 lsb//sec. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 lcst15 lcst14 lcst13 lcst12 lcst11 lcst10 lcst9 lcst8 d7 d6 d5 d4 d3 d2 d1 d0 lcst7 lcst6 lcst5 lcst4 lcst3 lcst2 lcst1 lcst0 high cst (hicstx) registers addresses: 0x06 (hicst1) 0x07 (hicst0) register update rate: f 0 /16 (~970 hz) scale factor: 80 lsb//sec the hicstx registers contain the unfiltered self-test information. the hicstx data can be used to supplement fault diagnosis in safety critical applications because sudden shifts in the self-test response can be detected. however, the cst bit of the fault register is not set when the hicstx data is observed to exceed the self-test limits. only the locstx memory registers, which are designed to filter noise and the effects of sudden temporary self-test spiking due to external disturbances, control the asser- tion of the cst fault bit. the data is presented as a 16-bit, twos complement number. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 hcst15 hcst14 hcst13 hcst12 hcst11 hcst10 hcst9 hcst8 d7 d6 d5 d4 d3 d2 d1 d0 hcst7 hcst6 hcst5 hcst4 hcst3 hcst2 hcst1 hcst0
ADXRS453 rev. 0 | page 24 of 32 quad memory (quadx) registers addresses: 0x08 (quad1) 0x09 (quad0) register update rate: f 0 /64 (~240 hz) scale factor: 80 lsb//sec equivalent the quadx registers contain a value corresponding to the amount of quadrature error present in the device at a given time. quadra- ture can be likened to a measurement of the error of the motion of the resonator structure and can be caused by stresses and aging effects. the quadrature data is filtered to f 0 /200 (~77.5 hz) and can be read frequently to detect sudden shifts in the level of quadrature. the data is presented as a 16-bit, twos complement number. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 qad15 qad14 qad13 qad12 qad11 qad10 qad9 qad8 d7 d6 d5 d4 d3 d2 d1 d0 qad 7 qad6 qad5 qad4 qad3 qad2 qad1 qad0 fault (faultx) registers addresses: 0x0a (fault1) 0x0b (fault0) register update rate: not applicable scale factor: not applicable the faultx registers contain the state of the error flags in the device. the fault0 register is appended to the end of every device data transmission (see table 10 ); however, this register can also be accessed independently through its memory location. the individual fault bits are updated asynchronously, requiring <5 s to activate, as soon as the fault condition exists on chip. when toggled, each fault bit remains active until the fault register is read or a sensor data command is received. if the fault is still active after the bit is read, the fault bit is immediately reasserted. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 unused fail amp ov uv d7 d6 d5 d4 d3 d2 d1 d0 pll q nvm por pwr cst chk 0 part id (pidx) registers addresses: 0x0c (pid1) 0x0d (pid0) register update rate: not applicable scale factor: not applicable the (pidx) registers contain a 16-bit number that identifies the version of the ADXRS453. combined with the serial number, this information allows for a higher degree of device individualization and tracking. the initial product id is r01 (0x5201), with sub- sequent versions of silicon incrementing this value to r02, r03, and so on. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 pidb15 pidb14 pidb13 pidb12 pidb11 pidb10 pidb9 pidb8 d7 d6 d5 d4 d3 d2 d1 d0 pidb7 pidb6 pidb5 pidb4 pidb3 pidb2 pidb1 pidb0 serial number (snx) registers addresses: 0x0e (sn3) 0x0f (sn2) 0x10 (sn1) 0x11 (sn0) register update rate: not applicable scale factor: not applicable the snx registers contain a 32-bit identification number that uniquely identifies the device. to read the entire serial number, two memory read requests must be initiated. the first read request to address 0x0e returns the upper 16 bits of the serial number, and the following read request to address 0x10 returns the lower 16 bits of the serial number. msb lsb d31 d30 d29 d28 d27 d26 d25 d24 snb31 snb30 snb29 snb28 snb27 snb26 snb25 snb24 d23 d22 d21 d20 d19 d18 d17 d16 snb23 snb22 snb21 snb20 snb19 snb18 snb17 snb16 d15 d14 d13 d12 d11 d10 d9 d8 snb15 snb14 snb13 snb12 snb11 snb10 snb9 snb8 d7 d6 d5 d4 d3 d2 d1 d0 snb7 snb6 snb5 snb4 snb3 snb2 snb1 snb0
ADXRS453 rev. 0 | page 25 of 32 package orientation and layout information 1 14 ADXRS453 (package front) 8 7 09155-033 figure 33. 14-lead ceramic lcc_v, vertical mount 9 .462 11.232 1.27 09155-034 0.572 1.691 figure 34. sample soic_cav sold er pad layout (land pattern), dimensions shown in millimeters, not to scale 09155-035 1.55 1.5 1.5 1 1 0.80.8 1.55 0.95 0.95 0.55 0.55 0.55 2.55 5.55 2.55 figure 35. sample lcc_v solder pad layout (land pattern) for vertical mounting, dimensions shown in millimeters, not to scale
ADXRS453 rev. 0 | page 26 of 32 1.50 0.50 0.90 0.80 1.50 1.00 3.10 2.70 7.70 09155-036 figure 36. sample lcc_v solder pad layout (land pattern) for horizontal mounting, dimensions shown in millimeters, not to scale
ADXRS453 rev. 0 | page 27 of 32 solder profile supplier t p t c supplier t p user t p t c user t p t c t p t l 25 t c ? 5c t s t smin t smax preheat area maximum ramp-up rate = 3c/sec maximum ramp-down rate = 6c/sec 09155-037 time 25c to peak t p t c ? 5c t l temperature time figure 37. recommended soldering profile table 18. recommended soldering profile limits profile feature sn63/pb37 pb-free average ramp rate (t l to t p ) 3c/sec max 3c/sec max preheat minimum temperature (t smin ) 100c 150c maximum temperature (t smax ) 150c 200c time (t smin to t smax ), t s 60 sec to 120 sec 60 sec to 120 sec ramp-up rate (t smax to t l ) 3c/sec max 3c/sec max time maintained above liquidous (t l ) 60 sec to 150 sec 60 sec to 150 sec liquidous temperature (t l ) 183c 217c classification temperature (t c ) 1 220c 250c peak temperature (t p ) t c + 0c/?5c t c + 0c/?5c time within 5c of actual peak temperature (t p ) 10 sec to 30 sec 20 sec to 40 sec ramp-down rate (t p to t l ) 6c/sec max 6c/sec max time 25c to peak temperatur e 6 minutes max 8 minutes max 1 based on ipc/jedec j-std-020d.01 for snpb an d pb-free proces ses. package volume < 350 mm 3 , package thickness > 2.5 mm.
ADXRS453 rev. 0 | page 28 of 32 package marking codes xrs453 beyz n #yyww lllllllll xrs453 brgz n #yyww lllllllll 09155-038 figure 38. lcc_v and soic_cav package marking codes table 19. package code designations marking meaning xrs angular rate sensor 453 series number b temperature grade (?40c to +105c) rg package designator (soic_cav package) ey package designator (lcc_v package) z rohs compliant n revision number # pb-free designation yyww assembly date code lllllllll assembly lot code (up to nine characters)
ADXRS453 rev. 0 | page 29 of 32 outline dimensions 072409-b 16 1 8 9 3.73 3.58 3.43 0.28 0.18 0.08 0.75 0.70 0.65 0.58 0.48 0.38 0.87 0.77 0.67 1.50 1.35 1.20 10.30 bsc 9.59 bsc 1.27 bsc 10.42 bsc 7.80 bsc 0.25 gage plane detail a detail a 8 4 0 c oplanarity 0.10 0.50 0.45 0.40 pin 1 indicator figure 39. 16-lead small outline, plastic cavity package [soic_cav] (rg-16-1) dimensions shown in millimeters 04-08-2010-a 1234567 1 23 45 6 7 14 13 12 11 10 9 8 9.20 9.00 sq 8.80 7.18 7.10 7.02 8.08 8.00 7.92 0.350 0.305 0.260 4.40 4.00 3.60 7.70 7.55 7.40 0.275 ref 1.175 ref 0.675 nom 0.500 min 0.50 typ 0.30 ref 0.30 ref c0.30 ref 1.70 ref (all pins) 1.70 ref (all pins) 1.00 (pins 2, 6) 1.40 (pins 1, 7, 8, 14) 0.60 (pins 3-5) 1.60 (pins 1, 7) 0.40 (pins 3-5, 10-12) 0.80 (pins 2, 6, 9, 13) 0.80 ref (metallization bump bump height 0.03 nom) bottom view (pads side) front v iew side view back view 0.35 ref 0.35 ref 89 10 11 12 13 14 r0.20 ref 1.50 (pins 2, 6) 1.00 (pins 9-10, 12-13) 0.80 (pins 10, 11, 12) do not solder center pads. figure 40. 14-terminal ceramic leadless chip carrier, vertical form [lcc_v] (ey-14-1) dimensions shown in millimeters
ADXRS453 rev. 0 | page 30 of 32 ordering guide model 1 , 2 , 3 temperature range package description package option ADXRS453beyz ?40c to +105c 14-terminal ceramic leadle ss chip carrier, vertical form [lcc_v] ey-14-1 eval-ADXRS453z evaluation board, soic_cav eval-ADXRS453z-v evaluation board, lcc_v eval-ADXRS453z-m analog devices inertial sensor evaluation system (includes ADXRS453 satellite) eval-ADXRS453z-s ADXRS453 satellite, standalone, to be used with inertial sensor evaluation system 1 z = rohs compliant part. 2 the tape and reel version of the ad xrs453beyz (14-terminal lc c_v) is releasing in the second quarter of 2011. 3 the ADXRS453brg (16-lead soic_cav) is releas ing in the second quarter of 2011.
ADXRS453 rev. 0 | page 31 of 32 notes
ADXRS453 rev. 0 | page 32 of 32 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09155-0-1/11(0)

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